VeriSilicon Launches ZSP5000 Vision Core Series for Edge Computing

Shanghai, China: VeriSilicon (688521.SH) has announced the launch of the ZSP5000 Digital Signal Processing (DSP) series IPs, built on its fifth-generation silicon-proven DSP architecture. This new product line is designed to deliver highly scalable and energy-efficient solutions for compute-intensive workloads, particularly in computer vision and embedded AI. The ZSP5000 series is tailored to meet the demands of various edge devices, ensuring both high performance and low power consumption.

The ZSP5000 series includes four variants: ZSP5000, ZSP5000UL, ZSP5000L, and ZSP5000H. These variants offer scalable vector processing performance, ranging from 32 to 256 8-bit Multiply-Accumulate (MAC) operations per cycle. For more demanding applications, VeriSilicon’s multi-core ZSP5400H can combine multiple ZSP5000H cores in a multi-cluster architecture to further enhance computing capabilities.

The ZSP5000 series boasts a rich and intuitive instruction set optimized for ease of programming and efficient performance tuning. Dedicated instructions accelerate common imaging and signal processing tasks, such as vector-scalar arithmetic, horizontal reductions, permutations, shifts, table lookups, clamping, and averaging. The series integrates the ZTurbo coprocessor interface, allowing customers to easily add custom instructions and hardware accelerators within the same pipeline. It is also compatible with the OpenCV Application Programming Interface (API), ensuring seamless integration with mainstream computer vision frameworks.

Additionally, the ZSP5000 series is equipped with a full-featured memory subsystem, a multi-channel 3D DMA engine, and a scalable multicore configuration, supporting flexible deployment for a wide range of applications. The series is backward compatible with VeriSilicon’s scalar ZSPNano series, making it suitable for handling mixed MCU and DSP workloads.

VeriSilicon provides comprehensive ZView development tools, including an Eclipse-based Integrated Development Environment (IDE), cycle-accurate simulator, optimizing compiler, debugger, and profiling tools, to streamline software development and system integration.

"With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series," said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. "It supports the industry-standard OpenCV API, enables streamlined interfacing with NPUs via our FLEXA interface, and integrates built-in audio processing capabilities for multi-modal applications. Energy efficiency is key at the edge, and the ZSP5000 series IPs feature an optimized memory access architecture to minimize processor power consumption. It also features ZTurbo, a custom instruction extension mechanism designed for targeted applications, which enables further power and performance optimization through seamless integration of hardware accelerators. Our leading customers are already leveraging these capabilities to achieve significant advancements in power and performance."

VeriSilicon is committed to providing customers with platform-based, all-around, one-stop custom silicon services and semiconductor IP licensing services, leveraging its in-house semiconductor IP. For more information, visit www.verisilicon.com.

The ZSP5000 series represents a significant step forward in the evolution of DSP technology for edge computing, offering a powerful, flexible, and efficient solution for a variety of applications.